1. Field of the Invention
The invention relates to data transmission, and more particularly to Serial-Peripheral-Interface (SPI) data transmission.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional system 100 for Serial-Peripheral-Interface (SPI) data transmission. System 100 includes an SPI controller 110 and an SPI slave 120. The SPI controller 110 is also referred to as an SPI master. After the SPI controller 110 receives data from a Peripheral Component Interconnect (PCI) bus, the SPI controller 110 transmits the received data to the SPI slave 120 according to SPI standard.
A data signal, a clock signal, and a chip select signal are transmitted between the SPI controller 110 and the SPI slave 120. The data signal comprises data transmitted from the SPI controller 110 to the SPI slave 120 according to SPI standard. The SPI slave 120 operates according to the clock signal, and operation of the SPI slave 120 is suspended if the clock signal is halted. The SPI controller 110 may control multiple SPI slaves and must specify the SPI slave 120 as the transmission target in advance. Thus, the SPI controller 110 enables the chip select signal to select the SPI slave 120 before data transmission between the SPI controller 110 and the SPI slave 120 is started.
The SPI controller 110 includes a buffer 112, and the SPI slave 120 includes a buffer 122 and a memory 124. FIG. 2 is a schematic diagram of signals communicated between the SPI controller 110 and the SPI slave 120 of FIG. 1. The SPI controller 110 first enables the chip select signal corresponding to the SPI slave 120, as shown by mark 210 of FIG. 2. The SPI controller 110 first stores data received from a PCI bus in the buffer 112. The SPI controller 110 then transmits an access command 202 and an address 204 through the data signal, wherein the access command 202 may be a write command and the address 204 specifies the writing address of data.
The SPI controller 110 then outputs data stored in the buffer 112 to the SPI slave 120 through the data signal 206. When the SPI slave 120 receives the data output by the SPI controller 110, the SPI slave 120 temporarily stores the received data in the buffer 122. When the SPI controller 110 estimates that the buffer 122 of the SPI slave 120 is full or when the SPI controller 110 wants to end the transmission, the SPI controller 110 disables the chip select signal, as shown by mark 220 in FIG. 2. When the chip select signal is disabled, the SPI slave 120 moves data stored in the buffer 122 to a memory 124 thereof. Thus, a data-transmission cycle between the SPI controller 110 and the SPI slave 120 is complete.
The SPI slave 120 stores data of the buffer 122 into the memory 124 when the SPI controller 110 disables the chip select signal. Storing data into memory 124, however, requires time and delays data transmission. Thus, the SPI controller 110 disables the chip select signal when the buffer 122 of the SPI slave 120 is full to save the transmission time. To fill the buffer 122 of the SPI slave 120 in one data-transmission cycle, the size of the buffer 112 of the SPI controller 110 is the same as that of the buffer 122 of the SPI slave 120. The buffer sizes of the buffers 112 and 122 are both assumed to be 256 bytes. If the SPI controller 110 disables the chip select signal when 1-byte data is transmitted, the transmission of 256-byte data requires 211.98 seconds. If the SPI controller 110 disables the chip select signal after 256-byte data is transmitted to fill the buffer 122 of the SPI slave 120, transmission of 256-byte data only takes 2.58 seconds.
Although the buffer sizes of the buffers 112 and 122 are the same, the conventional SPI data transmission still presents some drawbacks, such as the larger the memory 124 of the SPI slave 120 is, the larger the buffer 122 is required. It means an SPI controller 110 should comply with a buffer of the same size. In other words, SPI slaves with buffers of different sizes require different SPI controllers with buffers of different sizes for data transmission, and an SPI controller with fixed buffer size cannot control multiple SPI slaves with buffers of different sizes. If an SPI controller 110 controls an SPI slave 120 with a buffer size exceeding that of the SPI controller, the SPI controller 110 enables the chip select signal when data of the buffer 112 is completely transmitted, but the transmitted data cannot fill the buffer 122 of the SPI slave 120, causing extra delays in data transmission. Thus, a method for solving the problem of SPI data transmission is required.